Referring to FIG. 1, a block diagram of a circuit 10 illustrating a conventional phase locked loop circuit is shown. The circuit 10 includes a multiplexer 12, a number of dividers 14a and 14b and a phase lock loop (PLL) 16. Two or more inputs (i.e., paths IN1, IN2 and IN3) are presented to the multiplexer 12. One input is selected and presented as a reference signal REF, through the divider 14a, to the PLL 16. Another input is selected and presented as a feedback signal FB, through the divider 14b, to the PLL 16. Any one of the inputs (IN1, IN2, or IN3) could be implemented as the feedback signal FB or the reference signal REF. A second feedback signal or reference signal can be implemented from the input IN1, IN2, or IN3. The multiplexer 12 selects the desired input(s) to be used for the reference and feedback input paths to the PLL 16. The dividers 14a and 14b are implemented as digital counters or dividers before the PLL 16 to provide for frequency scaling of the reference and feedback signals. In some cases, the divider(s) 14a and/or 14b and the multiplexer 12 are not used.
The circuit 10 provides a PLL output frequency FOUT that is frequency and phase locked to the input reference signal REF. The frequency FOUT is determined by the integer ratio of the feedback to reference dividers 14a and 14b. Ideally the phase of whichever input is selected as the reference signal REF is equal to the phase of the input selected as the feedback signal FB. Phase error is determined from the difference in arrival times (skew) of either the rising or falling edge of the reference input REF relative to the feedback input FB.
Phase can be expressed in radians by dividing the skew by the period and multiplying by 2π (for radians) or 360° (for degrees). The term “skew” typically implies the long term or “average” time difference between signals. The terms “phase noise” or “jitter” are used to describe the dynamic variations in the arrival time between signals.
Disadvantages with the circuit 10 include (i) time delay differences through the dividers 14a and 14b and (ii) PLL 16 input skew errors. Such disadvantages contribute to input skew of the reference and feedback paths (i.e., skew does not equal zero). For example, a PLL typically uses an analog charge pump as part of the phase detection circuit. Analog mismatches cause skew at an input of the PLL to be non-zero. Time delay differences between the reference and feedback paths show up as non-zero phase skew at the PLL input as well. Furthermore, delay mismatches in the reference and feedback paths through the multiplexer 12 also cause phase skew. Mismatch within the long chain of required digital and analog circuitry for the reference and feedback paths (from the inputs IN1, IN2, IN3 to the charge pump in the PLL 16) is likely to cause input skew. Conventional analog charge pumps have one or more limitations such as P/N current mismatches and differences in charge injection.
Another conventional approach for correction of signal path delays in PLLs is to implement bang—bang digital control loops. Such control loops can be accurate, but are very slow. Conventional bang—bang control loops have a speed/jitter trade-off and can still have skew problems due to charge pump imbalance. Neither of these conventional techniques address time delays in counters and digital circuitry that occur before the PLL.